Professional RF Gain Block Amplifier for Wi-Fi Networks

1. System Specifications

Frequency Bands: 2.400–2.483 GHz & 5.150–5.825 GHz
Gain: 20 ± 1 dB
Noise Figure: ≤ 1.5 dB @ 2.4 GHz, ≤ 2 dB @ 5 GHz
Input/Output Impedance: 50 Ω
Input P_1dB: ≥ +10 dBm; Output P_1dB: ≥ +20 dBm
Supply: 5 V DC @ 60 mA
Return Loss: S11, S22 ≤ –12 dB
Stability: Unconditional (K > 1) from 0.1–6 GHz
PCB Substrate: FR-4, ε_r≈4.4, 1.6 mm

2. Active Device Selection

Parameter	Requirement	Device Chosen
NF @ 2.4 GHz	≤ 1.5 dB	Qorvo QPF4219 pHEMT
Gain @ 2.4 GHz	≥ 20 dB	22 dB (typ.)
P_1dB @ 2.4 GHz	≥ +20 dBm	23 dBm (typ.)
S-parameters	to 6 GHz	Available
DC Bias	5 V, 60 mA (Class A)	–

3. DC Bias Network

Class A bias: V_DD = 5 V, I_DQ ≈ 60 mA
Drain resistor R_D ≈ 50 Ω
Gate bias resistor R_G = 100 kΩ to ground
RF choke: 220 nH (0603) on V_DD
Bypass caps: 100 nF (0805) on V_DD and gate

4. Impedance Matching Networks

4.1 Input Match

Component	Value	Function
L_in (series)	2.8 nH	50 Ω → Z_in
C_{in_sh} (shunt)	1.5 pF	Flatten S11

4.2 Output Match

Component	Value	Function
L_out (series)	3.2 nH	Z_out → 50 Ω
C_{out_sh} (shunt)	1.2 pF	Flatten S22

4.3 Harmonic Traps

2nd harmonic trap: 8.2 nH ∥ 0.5 pF @ 4.8 GHz
3rd harmonic trap: 5.6 nH ∥ 0.3 pF @ 7.2 GHz

5. Bill of Materials

Ref.	Description	Value	Package	Qty
Q1	Qorvo QPF4219 pHEMT	–	QFN-16	1
C1–C2	RF coupling caps	2 pF	0402	2
Cin_sh	Input match shunt	1.5 pF	0402	1
Cout_sh	Output match shunt	1.2 pF	0402	1
Lin	Input series inductor	2.8 nH	0402	1
Lout	Output series inductor	3.2 nH	0402	1
Lb	RF choke	220 nH	0603	1
Rg	Gate bias resistor	100 kΩ	0603	1
Rd	Drain bias resistor	50 Ω	0603	1
Cb	DC bypass caps	100 nF	0805	2
Filters	Band-pass PCB filters	Custom	PCB	2

6. PCB Schematic

RF_IN ──[BPF]── C1 ── Lₐ ── Gate(Q1) ── Lₒ ── C2 ──[BPF]── RF_OUT
                │            Rg│             Rd│
               GND            Vcc           GND

Figure 1: Functional schematic showing input band-pass filter (BPF), coupling capacitors, matching inductors L_in/L_out, the QPF4219 amplifier stage, and output filter.

7. PCB Layout Guidelines

FR-4 substrate, 1.6 mm, ε_r=4.4.
50 Ω microstrip lines ~3 mm width on top layer.
Solid ground plane with via stitching every 3 mm.
Place RF choke and bypass caps within 0.5 mm of Q1 pins.
Keep matching components close to the transistor.
Use via pairs on shunt caps for minimal inductance.

8. Measurement & Verification

Network Analyzer: S-parameters, gain, return loss.
Spectrum Analyzer + Signal Generator: P_1dB, harmonics.
Noise Figure Analyzer: NF @ both bands.
Linearity: Two-tone OIP3, EVM under 802.11ac.
Temperature sweep: –20 °C to +70 °C stability.