Professional Wideband RF Gain Block Amplifier (0.1–50 MHz)

Introduction

This document describes the design, simulation, PCB layout, and testing procedures for a two-stage wideband RF gain block amplifier covering 0.1 to 50 MHz. The amplifier delivers 24 dB of flat gain, maintains a noise figure below 3 dB, and operates unconditionally stably from a single 5 V supply.

Project Objectives

The goal is to amplify HF signals up to 50 MHz with flat gain, low noise, and minimal distortion. The amplifier interfaces directly to 50 Ω systems, consumes less than 25 mA total, and uses internally matched MMIC devices to eliminate external matching networks.

System Specifications

Frequency range: 0.1–50 MHz
Small-signal gain: 24 dB ±1 dB
Noise figure: ≤ 3 dB total
Input/output impedance: 50 Ω
Input P_{1 dB}: ≥ +10 dBm; Output P_{1 dB}: ≥ +15 dBm
IIP3: > +10 dBm
Supply voltage: 5 V DC @ <25 mA
Stability: Unconditional (Rollett’s K > 1)
PCB substrate: FR-4, ε_r ≈ 4.4, thickness 1.6 mm

Active Device Selection

Two Mini-Circuits PSA4-5043+ MMICs in SOT-23-6 are cascaded. Each device provides 12 dB gain, a 2 dB noise figure, and DC–500 MHz bandwidth at a 5 V, 10 mA bias. Cascading yields approximately 24 dB of flat gain with excellent linearity.

Circuit Architecture & Biasing

Each MMIC stage is biased in class A. The 5 V rail feeds through a 220 nH RF choke to isolate the supply from RF, and a 100 nF bypass capacitor placed next to each device pin ensures a low-impedance path to ground at HF. No external bias resistors are required, as the PSA4-5043+ integrates its bias network and maintains a 50 Ω match internally.

RF Coupling & Filtering

220 nF coupling capacitors at the input, inter-stage, and output provide AC coupling down to 0.1 MHz. Optional dual T-section band-pass filters on the PCB can be added at the input and output to suppress out-of-band signals and protect against strong broadcast interference.

Simulation & Verification

The full schematic is imported into ADS or LTspice with S-parameter models for the PSA4-5043+ and filter components. An AC sweep from 10 kHz to 100 MHz verifies gain flatness, return loss, noise figure, and unconditional stability (Rollett’s K factor). Two-tone simulations at representative HF frequencies evaluate IIP3 linearity.

PCB Layout Guidelines

Layout is optimized on FR-4 with 50 Ω microstrip traces (≈ 3 mm width), though impedance control is relaxed below 50 MHz. Critical components—MMICs, chokes, bypass and coupling capacitors—are placed within 1 mm of each other. A continuous ground plane and via stitching every 5 mm ensure low ground impedance.

Bill of Materials

2 × Mini-Circuits PSA4-5043+ (SOT-23-6)
4 × 220 nF coupling capacitors, 0805, 6.3 V
2 × 220 nH RF chokes, 0603
2 × 100 nF bypass capacitors, 0805, 10 V
Optional filter parts: inductors and capacitors for T-section filters

Testing Procedures

After prototyping, measure S-parameters with a network analyzer to confirm gain, return loss, and P_{1 dB}. Measure noise figure across 0.1–50 MHz with a noise-figure analyzer. Perform two-tone IIP3 testing on a spectrum analyzer. Verify stability by sweeping from DC to 500 MHz and ensure no oscillations. Conduct temperature tests from –20 °C to +70 °C.

ASCII Schematic Diagram

           RF_IN ── C_in1 ──[PSA4-5043+]── C_coup ──[PSA4-5043+]── C_out2 ── RF_OUT
                     │         │            │         │
                    GND       CHK1         CHK2      GND
                               │            │
                              VCC          VCC
                     C_bp1     │            │     C_bp2
                     │         │            │     │
                    GND       GND          GND   GND

      Legend:
      C_in1/C_out2 – 220 nF coupling capacitors
      C_coup       – 220 nF interstage coupling capacitor
      CHK1/CHK2    – 220 nH RF choke on supply line
      C_bp1/C_bp2  – 100 nF DC bypass capacitors
      [PSA4-5043+] – MMIC amplifier, 12 dB gain, DC–500 MHz